Classic 5-stage Pipeline

out of order instruction completion

Superpipelined & Superscalar

Branch Prediction

Static instruction scheduling

enforcing data dependencies: Tomasulo algorithm

Speculative execution: Execution beyond unresolved branches

Adding Speculation to Tomasulo alogrithm

Dynamic memory disambiguation

Explicit register renaming

Checking pointing

Register fetch after instruction issue

speculative instruction scheduling

memory disambiguation

beating the data-flow limit: value prediction

multiple instructions per clock

deal with complex ISAs

Duality of Dynamic and Static Techniques

VLIW Architecuture

Loop Unrolling

Software pipelining

Non-cyclic VLIW Scheduling

Predicated Execution

Speculative memory disambiguation

Exception

Memory access locality

Memory hierarchy coherence

Memory inclusion

Cache mapping and organization

Replacement policies

Write policies

Cache hierarchy performance

Classification of cache miss

non-blocking (look-up free) caches

Cache prefetching and preloading

Motivation for virtual memory

Operating Systems' View of Virtual Memory

Virtual Address Translation

Memory Access Control

Hierarchical Page Tables

Inverted page table

Translation Lookaside Buffer

VIrtual-address caches with physical tags

Virtual-address caches with virtual tags

Shared-memory communication model

Hardware components

why is coherence in multiprocessors so hard

Cache Protocols

Memory access atomicity

Plain Coherence

Formal model for sequential consistency

Access ordering rules for sequential consistency

Memory access buffering

Basic synchronization primitives

Hardware-based synchronization

Software-based synchronization

Not relying on synchronization

Relaying on synchronization

Conservative memory model enforcement in OoO processors

Speculative violations of memory orders

processors

memory

interconnects

Instruction-level parallelism (ILP)

Thread-Level Parallelism (TLP)

Vector and array processors

Benchmarking

Reporting performance for a set of programs

Reporting speedups

Amdahl's law

Parallel speedup

Power and energy

Reliabiligy

Wire Delays

Design Complexity

Limits of miniaturization and the CMOS end-point