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Chapter 6 Bus
This is a mind map about Chapter 6 Bus. A bus is a set of public information transmission lines that can be shared by multiple components in a time-sharing manner.
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Chapter 6 Bus
- bacteria
This is a mind map about bacteria, and its main contents include: overview, morphology, types, structure, reproduction, distribution, application, and expansion. The summary is comprehensive and meticulous, suitable as review materials.
- Plant asexual reproduction
This is a mind map about plant asexual reproduction, and its main contents include: concept, spore reproduction, vegetative reproduction, tissue culture, and buds. The summary is comprehensive and meticulous, suitable as review materials.
- Reproductive development of animals
This is a mind map about the reproductive development of animals, and its main contents include: insects, frogs, birds, sexual reproduction, and asexual reproduction. The summary is comprehensive and meticulous, suitable as review materials.
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- Outline
Chapter 6 Bus
bus
Bus overview
Basic concepts of bus
bus definition
A bus is a set of public information transmission lines that can be shared by multiple components in a time-shared manner.
Two characteristics
time sharing
shared
bus device
main device
slave device
Bus characteristics
Mechanical properties (size, shape)
Electrical characteristics (transmission direction and effective level range)
Functional characteristics (function of each transmission line)
Time characteristics (relationship between signals and timing)
Classification of buses
On-chip bus
The common connection line between the internal registers of the CPU chip and between the registers and the ALU.
system bus
Data bus (bidirectional)
The data can be real data, instruction code or status information, and sometimes it can even be a control information.
Address bus (unidirectional)
Used to give the address of the source or destination data on the data bus in the main memory unit or I/O port.
control bus
Control line (one way)
Status line (one-way)
For a certain signal line, it is one-way transmission, but for the whole, it is two-way transmission.
I/O bus
It is used to connect medium and low-speed I/O devices and is connected to the system bus through the I/O interface.
Communication bus (external bus)
Enable data communication between computer systems or computers and other systems (such as control instruments, mobile communications, etc.).
System bus structure
Single bus structure
The single-bus structure hangs the CPU, main memory, and I/O devices (through the I/O interface) on a set of buses, allowing the direct exchange of information between I/O devices and between I/O devices and main memory.
Note that after the DMA controller appears, the CPU is no longer the only master device. The DMA controller can also apply for system bus usage rights as a master device.
Dual bus structure
The main memory bus (host bus) connects fast modules such as CPU and main memory. The I/O bus connects slow devices such as keyboards and printers.
The memory controller is a dual-port memory controller that connects the memory bus and the system bus at the same time.
The CPU accesses the main memory through the storage bus, and accesses external devices through the system bus. Data transfers between external devices and main memory, and between the CPU and main memory, can occur in parallel.
Three bus structure
Common bus standards
Commonly used on-chip buses
AMBA bus
Wishbone bus
Common system buses
ISA
MCA
PCI
Common I/O buses
AGP
PCI Express
SCSI
SAS bus
Commonly used external buses
RS-232-C and RS-485
USB
Bus performance indicators
Bus transfer cycle
Bus clock cycle
Bus operating frequency
bus clock frequency
bus width
bus bandwidth
Bus multiplexing
Number of signal lines
Bus transactions and timing
bus transaction
request phase
arbitration stage
addressing phase
transmission phase
release phase
Synchronous timing mode
A unified clock signal is used to coordinate the transmission timing relationship between the sending and receiving parties.
Asynchronous timing mode
Timing control is achieved entirely by transmitting "handshake" signals that restrict each other.
Divide the two components or devices that exchange information into master devices and slave devices.
Depending on whether the revocation of the "request" and "reply" signals is interlocked, the asynchronous timing method is divided into the following three types:
No interlocking mode
The request signal of the master device will be automatically canceled after t1 time.
The response signal will also be automatically canceled after t2 time.
Semi-interlocking method
The cancellation of the request signal depends on the establishment of the response signal, which requires two handshakes.
After the slave device response signal ACK is sent out, it will be automatically canceled after t2 time has elapsed.
Full interlocking method
The cancellation of the reply signal depends on the cancellation of the request signal.
Asynchronous control in read data cycle