Advantages: Various I/O devices are connected to the I/O bus through the I/O interface, making it easier to add and delete devices.

Disadvantages: This structure still occupies the CPU when the I/O device exchanges information with the main memory, so it also affects the CPU's work efficiency.

Advantages: When the I/O device exchanges information with the main memory, in principle, it does not affect the CPU work, and the CPU can still continue to process operations that do not access storage or I/O devices. This improves the efficiency of the CPU

Disadvantages: There is only one set of buses. When each component wants to occupy the bus at a certain time, conflicts will occur.

Advantages: On the basis of the single bus, a bus between the CPU and the main memory is opened up, called the storage bus. This group of buses has high speed and is only used to transmit information between the main memory and the CPU, which not only improves the transmission efficiency , reducing the burden on the system bus, and retaining the feature of exchanging information between I/O devices and memory without going through the CPU.

Disadvantage: conflicts can occur when exchanging information

The characteristics of the dual bus structure are to separate the lower I/O equipment from the single line to form a structure that is separated from the storage bus from the I/O bus, and the response speed has changed

Subtopic storage bus is used for transmission between CPU and storage. I/O bus is used to transfer information between CPU and various I/O devices. DMA bus is used to directly exchange information between high-speed I/O devices and storage. Among the three line structures, only one bus can be used at any time. The storage bus and the DNA bus cannot access the components at the same time. The I/O bus can only be used when the CPU executes I/O instructions.

Parallel transfer bus

serial transmission bus

8-bit transmission bus

16-bit transmission bus

32-bit transfer bus

peripheral bus

Measurement and control bus

network communication bus

On-chip bus

system bus

communication bus

data bus

address bus

control bus

①Bus width: usually refers to the number of data buses, expressed in bits, such as 8-bit, 16-bit, 32-bit, 64-bit (i.e. 8, 16, 32, 64).

②Bus bandwidth: Bus bandwidth can be understood as the data transmission rate of the bus, that is, the number of bits of data transmitted on the bus per unit time. It is usually measured by the number of bytes of information transmitted per second. The available unit is MBps (megabytes per second). express. For example, if the bus operating frequency is 33 MHz and the bus width is 32 bits (4B), the bus bandwidth is 33x(32÷8)=132 MBps.

③Clock synchronization/asynchronous: The bus where the data on the bus works synchronously with the clock is called a synchronous bus, and the bus which works asynchronously with the clock is called an asynchronous bus.

④Bus multiplexing: Two signals are transmitted in a time-shared manner on one signal line. For example, usually the address bus and the data bus are physically separate buses. The address bus transmits address codes, and the data bus transmits data information. In order to improve the utilization of the bus and optimize the design, the address bus and the data bus share a set of physical lines, and the address signals and data signals are transmitted in a time-sharing manner on this set of physical lines, which is the multiplexing of the bus.

⑤ Number of signal lines: the sum of the three bus numbers: address bus, data bus and control bus.

⑥Bus control mode: including burst work, automatic configuration, arbitration mode, logic mode, counting mode, etc.

⑦Other indicators: such as load capacity, power supply voltage (whether 5V or 3.3V is used), whether the bus width can be expanded, etc.

Application allocation stage

addressing phase

transfer phase

end stage

Synchronous communication

Asynchronous communication

semi-synchronous communication

Separate communication