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MindMap Gallery Chapter 7 Input and Output System

Chapter 7 Input and Output System

This is a mind map about Chapter 7 Input-Output System. The main task of the input-output system is to receive external input information and convert the information into a form that can be processed internally by the computer.

Edited at 2024-01-16 15:51:57

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Chapter 7 Input and Output System

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Outline

Mind map of computer composition principles
- 10
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Computer composition principles
- 9
- 1
- 1
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How the program runs
- 13
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Chapter 1 Computer System Overview
- 18
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Chapter 6 Bus
- 11
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Chapter 2 Data Representation and Operation
- 6
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Chapter 3 Storage System
- 8
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Chapter 4 Command System
- 15
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Chapter 5 Central Processing Unit
- 19
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Chapter 7 Input/Output System

input/output system

Basic concepts of I/O system

I/O control mode

Mainly used for external devices with low data transfer rate

Program query method

Program interrupt mode

Mainly used for devices with high data transfer rates

DMA mode

channel mode

external device

input device

output device

External memory (auxiliary storage)

I/O interface

I/O interface functions

Perform address decoding and device selection

Realize communication control between host and peripherals

Implement data buffering (the interface must set up a data buffer register for temporary storage of data to avoid data loss due to inconsistent speeds.)

Signal format conversion

Transmit control commands and status information

Basic structure of I/O interface

Data Buffer Register (DBR): Used to buffer data to match the speed difference between the CPU and external devices.

Device Status Register (DSR): used to feedback device status, common status information such as device busy, device ready, device error, etc. In the program query mode, the CPU determines the status of the device by reading the status register.

Device command register (DCR): used to receive device control commands sent by the CPU, such as device reset, device identification, read and write control, etc. Different devices can support different commands. Simple devices do not even have command registers, such as simple keyboard input and character terminal output devices. Sometimes the status and command registers are combined into one.

The status register and the control (command) register are opposite in the transfer direction.

Through the data bus, data is transferred between the data buffer register and the memory or CPU register. At the same time, the status information of the interface and the device is recorded in the status register, and the status information is sent to the CPU through the data line. The CPU's control commands for peripherals are also transmitted through the data line, usually to the control register of the I/O interface.

The address line in the interface is used to give the address of the register in the I/O interface to be accessed. It is sent to the control logic component of the I/O interface together with the read and write control signals.

The read and write signals transmitted through the control line confirm whether to read the register or write the register. In addition, the control line also transmits some arbitration signals and handshake signals.

Access operations to the data buffer register and status control register are completed through corresponding instructions, which are usually called I/O instructions.

Type of I/O interface

Control method for accessing I/O devices by host

Program query interface

Interrupt interface

DMA interface

I/O ports and their addressing

I/O ports refer to registers in the interface circuit that can be directly accessed by the CPU.

data port

status port

control port

Addressing

Unified addressing

There is no need to set up dedicated I/O instructions. External devices can be accessed using Load/Store instructions. The specific device to be accessed depends on the address.

Independent addressing

Special I/O instructions must be used to access external devices.

Different instructions generate different bus control signals to identify whether the address on the address bus is a main memory or I/O address.

A computer system includes multiple I/O devices, all of which are connected to the bus through the "I/O interface (bus interface)". The CPU uses the device address to communicate with the I/O interface through the bus to access the I/O devices. The I/O interface is the physical and logical interface that connects the bus and I/O devices, including both physical connection circuits and logical interfaces for software interaction.

I/O mode

Program query method

The control of information exchange is completely implemented by the CPU execution program.

There are two main strategies for polling

busy waiting

The CPU cannot perform other tasks and is called a busy wait state.

Once the device is ready the CPU can query the sense.

Regular polling

Start a scheduled interrupt.

Program interrupt mode

The CPU arranges in the program to start a certain peripheral at a certain time, and then the CPU continues to execute the current program without waiting for the peripheral to be ready like the query method.

Save breakpoints. In order to ensure that the original program can be returned correctly after the interrupt service routine is executed, the breakpoint of the original program (the contents of the PC and PSW that cannot be directly read by the instruction) must be saved in the stack or a specific register.

Exit the interrupt service routine. Identify the interrupt source and send the corresponding service program entry address to the program counter PC.

Save scenes and masks and set new masks. After entering the interrupt service routine, you must first save the scene and interrupt mask word. The scene information refers to the content of the working register visible to the user, which stores the current value of the program execution to the breakpoint.

An interrupt occurs every time data is transmitted.

Typical structure of interrupt service routine

Distinguish between interrupt response and interrupt service routine

I/O control flow in program interrupt mode

Interrupt processing procedure

DMA mode

Simple DMA controller

main memory address counter

Transfer length counter

data buffer register

When the DMAC is a slave device, it can be used to receive data transmitted by the CPU. When the DMAC is a master device, it can be used to temporarily store the transmitted data. Of course, if the data exchange between the device and the memory is realized directly through the data bus without going through this register, the performance will be better.

DMA request trigger

"Control/State" logic

Interruption mechanism

During the DMA transfer process, the DMA controller will take over the address bus, data bus and control bus of the CPU, and the use of the CPU's main memory control signal is prohibited.

Data does not need to be transferred by CPU registers.

DMA transfer process

Memory contention problem (DMA transfer method)

Stop the CPU from accessing memory

Continuously occupy several bus cycles for data transfer.

In this transfer method, when a batch of data needs to be transferred, the DMA interface issues a bus usage request (HRQ) to the CPU. After the CPU gives up the bus control rights (represented by HLDA), the DMA interface controls the bus for data transfer until all data transfers are completed. When, bus control is released.

DMAC and CPU alternately access memory

This method divides the memory access cycle (machine cycle) into two segments, one segment is dedicated to DMAC access to memory, and the other segment is dedicated to CPU access to memory.

Divide a CPU cycle into two cycles, C1 and C2, where C1 is exclusively for DMA memory access and C2 is exclusively for CPU memory access.

The DMA interface does not need to apply for and release bus usage rights, and the transmission efficiency is high. The CPU does not need to pause program execution, and the work efficiency is very high.

cycle appropriation

Only when DMAC needs to access memory, the CPU pauses a storage cycle for DMAC to access the main memory. After the transfer of a data (word or machine word) is completed, bus control is returned to the CPU.

Whenever the peripheral is ready, the DMA interface makes a bus use request to the CPU. After the CPU gives up bus control, the DMA interface controls the bus to transmit data, and releases the bus control after each data transfer.

The response to a DMA request can occur at the end of any machine cycle (after instruction fetch, indirect address, or execution cycle).