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MindMap Gallery Chapter 3 Storage System
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Chapter 3 Storage System
This is a mind map about Chapter 3 Storage System, including memory overview, main memory, connection between main memory and CPU, external memory, etc.
Edited at 2024-01-16 15:52:21
- cáncer de pulmón
El cáncer de pulmón es un tumor maligno que se origina en la mucosa bronquial o las glándulas de los pulmones. Es uno de los tumores malignos con mayor morbilidad y mortalidad y mayor amenaza para la salud y la vida humana.
- diabetes
La diabetes es una enfermedad crónica con hiperglucemia como signo principal. Es causada principalmente por una disminución en la secreción de insulina causada por una disfunción de las células de los islotes pancreáticos, o porque el cuerpo es insensible a la acción de la insulina (es decir, resistencia a la insulina), o ambas cosas. la glucosa en la sangre es ineficaz para ser utilizada y almacenada.
- sistema digestivo
El sistema digestivo es uno de los nueve sistemas principales del cuerpo humano y es el principal responsable de la ingesta, digestión, absorción y excreción de los alimentos. Consta de dos partes principales: el tracto digestivo y las glándulas digestivas.
Chapter 3 Storage System
- cáncer de pulmón
El cáncer de pulmón es un tumor maligno que se origina en la mucosa bronquial o las glándulas de los pulmones. Es uno de los tumores malignos con mayor morbilidad y mortalidad y mayor amenaza para la salud y la vida humana.
- diabetes
La diabetes es una enfermedad crónica con hiperglucemia como signo principal. Es causada principalmente por una disminución en la secreción de insulina causada por una disfunción de las células de los islotes pancreáticos, o porque el cuerpo es insensible a la acción de la insulina (es decir, resistencia a la insulina), o ambas cosas. la glucosa en la sangre es ineficaz para ser utilizada y almacenada.
- sistema digestivo
El sistema digestivo es uno de los nueve sistemas principales del cuerpo humano y es el principal responsable de la ingesta, digestión, absorción y excreción de los alimentos. Consta de dos partes principales: el tracto digestivo y las glándulas digestivas.
- Recommended to you
- Outline
Chapter 3 Storage System
Storage System
Memory overview
Classification of memory
Function (level) classification
main memory
auxiliary memory
cache memory
Access method classification
Random Access Memory (RAM)
Read Only Memory (ROM)
serial access memory
Sequential Access Memory (SAM) (such as tape)
Direct Access Memory (DAM) (such as disk, CD)
information preservation classification
volatile memory
non-volatile memory
Memory performance indicators
storage
unit cost
Storage speed
Multi-level storage system
The information in each level of memory is an inclusive relationship
Cache-main memory layer
Mainly solves the problem of CPU and main memory speed mismatch
Data transfer between main memory and Cache is automatically completed by hardware and is transparent to all programmers.
Main memory-auxiliary memory layer
Mainly solves the capacity problem of storage system
Data transfer between main memory and auxiliary memory is completed by the hardware and operating system, and is transparent to the application programmer.
In the Cache-main memory layer and the main memory and auxiliary memory layer, the contents in the upper layer are just copies of the contents in the next layer, that is, the contents in Cache (or main memory) are only main memory (or auxiliary memory). part of the content.
Storage of data in main memory
Main memory is usually addressed on a byte-by-byte basis. Taking a 32-bit computer as an example, the main memory can be accessed in bytes, 16-bit half words, or 32-bit words.
Data boundary alignment
It is theoretically possible to start from any byte address, but when a multi-byte variable is spread across different word storage units, accessing the variable requires multiple storage cycles.
The so-called boundary alignment means boundary alignment according to the size of the data type. The specific rules are as follows.
(1) The last 3 bits of the starting byte address of eight-byte data are 000, and the address is an integer multiple of 8. (2) The lowest two bits of the starting byte address of four-byte data are 00, and the address is an integer multiple of 4. (3) The lowest bit of the starting byte address of double-byte data is 0, and the address is an integer multiple of 2. (4) There is no boundary alignment problem for single-byte data (main memory is addressed by byte).
main memory
SRAM chips and DRAM chips
How SRAM works
The storage element uses a bistable flip-flop (six-transistor MOS)
non-destructive readout
How DRAM works
Use the charge on the gate capacitor in the memory cell circuit to store information
Refresh method
Centralized refresh
In a refresh cycle, a fixed period of time is used to regenerate all rows of the memory one by one.
The advantage is that read and write operations are not affected by refresh work. The disadvantage is that the memory cannot be accessed during the concentrated refresh period (dead zone).
Scattered refresh
The access cycle of the memory chip is 0.5μs, and the access cycle of the system is 1μs.
The system duty cycle of a memory is divided into two parts: The first half is used for normal reading, writing or holding. The second half is for refresh.
The advantage is that there is no dead zone. The disadvantage is that it lengthens the access cycle of the system and reduces the speed of the entire machine.
Asynchronous refresh
Asynchronous refresh is a combination of the first two methods. It can shorten the "dead time" and make full use of the maximum refresh interval of 2ms.
Divide the refresh cycle by the number of rows to obtain the time interval t between two refresh operations, and use a logic circuit to generate a refresh request every time t.
This prevents the CPU from waiting continuously for too long and reduces the number of refreshes, fundamentally improving the work efficiency of the entire machine.
DRAM chip read and write cycle
Comparison of SRAM and DRAM
Internal structure of memory chip
Memory bank (memory matrix)
address decoder
I/O control circuit
Chip select control signal
Read/write control signals
ROM
Characteristics of read-only memory (ROM)
Both ROM and RAM support random access memory.
The structure is simple, so the bit density is higher than that of read-write memory.
It is non-volatile and therefore highly reliable.
ROM type
mask mode rom
one time programmable read only memory
erasable programmable read-only memory
Flash memory
Solid State Drives (SSD)
Basic components of main memory
Multi-module memory
Single multi-word memory
The structure of a single multi-word memory is exactly the same as the memory bit expansion method. In this method, multiple memory modules share the address bus and access the same unit of different memory modules in parallel according to the same address, thereby achieving access to multiple memories in the same memory cycle. words, if m storage modules work concurrently, the main memory bandwidth can be increased by m times.
The most common multi-channel memory technology currently used in computers is the single-body multi-word technology.
Read out m words in parallel at a time (the bus width is also m words).
In one access cycle, m instructions are fetched from the same address, and then the instructions are sent to the CPU for execution one by one. That is, every 1/m access cycle, the CPU fetches an instruction from the main memory.
Disadvantages: Instructions and data must be stored continuously in the main memory. Once a transfer instruction is encountered, or the operands cannot be stored continuously, the effect of this method is not obvious.
multi-body parallel memory
High-order interleaved addressing (sequential mode)
The main purpose is to expand the memory capacity, which is exactly the same as memory word expansion.
Low-order interleaved addressing (interleave mode)
The lowest address in the same body is the same
Main memory to CPU connection
Connection principle
Expansion of main memory capacity
bit extension method
word expansion method
simultaneous grapheme expansion
Address allocation and chip selection of memory chips
Line selection method
The line selection method uses high-order address lines other than on-chip addressing to be directly connected (or via inverters) to the chip select terminals of each memory chip. When the information of a certain address line is "0", the corresponding address line is selected. memory chip.
Disadvantages: The address space is not continuous.
decoding chip selection method
Eight 8Kx8-bit memory chips are used to form a 64Kx8-bit memory (the address line is 16 bits and the data line is 8 bits), which requires 8 chip select signals.
If the line selection method is used, except for the 13-bit address line for on-chip addressing, only the upper 3 bits remain, which is not enough to generate 8 chip select signals.
Memory to CPU connection
Reasonable selection of memory chips
Address line connection
The number of address lines of the CPU is often greater than the number of address lines of the memory chip. Usually the low bit of the CPU address line is connected to the address line of the memory chip. You can wait.
Data cable connection
When not equal, the memory chip must be expanded so that the number of data bits is equal to the number of data lines of the CPU. Must be equal.
Read/write command line connections
Chip select line connection
The chip select valid signal is related to the CPU's memory access control signal MREO (active low level).
If the CPU accesses I/O, MREO is high, indicating that memory work is not required.
The control lines of the SRAM chip include chip select signals and read and write control lines.
DRAM does not have a chip select control line. When expanding capacity, RAS and CAS can be used to control chip selection.
external memory
disk storage
Disk device components
Hard disk storage composition
Disk drive
The disk drive is also called a disk machine. Its main function is to use electrical signals to drive the disk platter to complete magnetic operations. It consists of three parts: spindle drive, positioning drive and data control.
disk controller
The main function is to receive disk operations from the host, implement drive control, and implement read/write control. The hardware is mainly composed of host interface, device interface control circuit, data buffer, data control circuit, data separation circuit, etc.
platter
The main function is to store data. Hard drives usually have multiple platters, all fixed on the spindle. They all use uniform rotation during operation, so the recording density of the inner track is higher than the recording density of the outer track.
storage area
Heads
Cylinders
Sectors
Principles of magnetic recording
Read/write operations are completed through electromagnetic conversion.
Disk performance indicators
recording density
disk capacity
average access time
The average access time consists of three parts: seek time (the time it takes for the magnetic head to move to the destination track), rotation delay time (the time it takes for the magnetic head to position the sector to be read and written), and transmission time (the time it takes to transmit data). Since the distance between seeking and finding sectors varies, the seek time and rotation delay time are usually averaged. (The real exam sometimes also gives the latency of the disk controller.)
data transfer rate
disk address
The working process of hard disk
addressing
Read disk
write disk
Disk Array
Organize multiple independently operating disks into an array in a certain way, and use data blocking technology to stagger and store data on different disks so that they can work in parallel to improve access speed.
RAID improves transfer rates by using multiple disks simultaneously
Dramatically increase storage system data throughput by parallelizing access across multiple disks
Not only expands storage capacity but also improves disk data access speed
Cross storage, parallel access
Improve reliability
Improve security and reliability through mirroring function
Provide fault tolerance through data verification
SSD
composition
One or more flash memory chips (similar: disk drive)
Flash translation layer (similar: disk controller translates logical block read and write requests from the CPU into read and write control signals for the underlying physical device)
Data is read and written in page units.
A page can only be written to after the entire block to which it belongs has been erased.
However, once a block is erased, each page in the block can be written directly again.
Random writes are slow for two reasons
Erase blocks are slower.
If a write operation attempts to modify a page P that contains existing data, then all pages containing useful data in this block must be copied to a new (erased) block before writing to page P can occur.
Advantages and Disadvantages
advantage
Random access is much faster than mechanical disks
No mechanical noise or vibration
Lower energy consumption
Good earthquake resistance
High security
shortcoming
easy to wear
cache memory
The locality principle of program access
temporal locality
The information that will be used in the near future is likely to be the information that is being used now, because there are loops in the program.
Specific to array elements, if the array element is accessed only once, there must be no temporal locality.
spatial locality
The information to be used in the near future is likely to be adjacent in storage space to the information being used now, because instructions are usually stored and executed sequentially, and data are generally stored in clusters in the form of vectors, arrays, etc. together.
The basic working principle of Cache
Both the Cache and the main memory are divided into equal-sized blocks. The number of blocks in the Cache is much less than the number of blocks in the main memory. It only saves copies of the most active blocks in the main memory.
The data exchange between CPU and Cache is in units of words, while the data exchange between Cache and main memory is in Cache blocks.
When the CPU issues a read request
If the memory access address is hit in the Cache, this address is converted into a Cache address, and the Cache is read directly, regardless of the main memory.
If the cache misses, the main memory still needs to be accessed, and the block where the word is located is transferred from the main memory to the cache at one time.
If the cache is full at this time, this block needs to be used to replace an original block of information in the cache according to a certain replacement algorithm.
In the end, Cache is accessed
When the CPU issues a write request
If the cache hits, it needs to be processed according to a certain write strategy. Common processing methods include full write and write back.
When missing, the write allocation method writes the data into the Cache, and the non-write allocation method directly writes the data back to the main memory.
Cache and main memory mapping method
direct mapping
Cache line number = main memory block number mod total number of Cache lines
fully associative mapping
any position
Use G comparators to compare all Cache lines simultaneously.
set associative mapping
Cache group number = main memory block number mod Cache group number (Q)
Two-way group connection
Each cache line corresponds to a marked entry
Including valid bit, tag bit, consistency maintenance bit, replacement algorithm control bit
Cache write strategy
For Cache write hit (write hit)
Full write method (write-through method, write-through)
When a cache write hits, the same data block in the cache and main memory is modified at the same time.
The disadvantage of the write-through method is that the cache has no buffering function for CPU write operations, which reduces the efficiency of the cache.
write-back
Each cache line sets a modification bit (dirty bit).
This strategy makes the cache act as a cache for both read and write operations.
For Cache write miss
Write-allocate (write-alocate)
Load the block in main memory into the Cache, and then update the Cache block.
Non-write-allocate (not-write-allocate)
Only writes to the main memory, no block adjustment is performed.
virtual memory
Basic concepts of virtual memory
Virtual memory uniformly addresses the address space of main memory or auxiliary memory to form a huge address space. In this space, users can program freely without caring about the actual main memory capacity and the actual storage location of the program in the main memory. .
Main memory and auxiliary memory together constitute virtual memory, and both work under the joint management of hardware and system software.
Typical organizational structure of virtual memory
virtual address (virtual address)
Virtual memory page number Page word address
Main memory physical address (real address)
Main memory page number Page word address
The CPU accesses the main memory with a virtual address, uses the memory management control unit MMU (Memory Management Unit) to find the correspondence between the virtual address and the physical address, and determines whether the content corresponding to the virtual address is already in the main memory.
Disk storage address (disk address or auxiliary storage address)
Disk number Disk number Track number Sector number
How virtual memory works
The virtual memory-to-main memory address conversion must be completed by the MMU. When the conversion fails, an exception signal is generated, triggering the execution of the page missing exception handler to complete the remaining work, and re-executing the instruction that generated the page missing exception to ensure that the program is executed correctly.
In the end, the data is obtained from the main memory, and the CPU cannot directly access the auxiliary memory.
Paged virtual memory
In most systems, there is one page table for each process.
page table
Page table logical structure diagram
Both main memory and disk are divided into fixed-size pages
The disk is divided into swap partition and data partition
The swap partition is used to store dynamically modified data swapped out of main memory pages.
Data partition is used to store user programs and data
The main memory and disk space are combined to form the virtual address space.
Page virtual memory access process
When a page hits, the steps performed by the CPU hardware
The processor generates a virtual address and passes it to the MMU.
The MMU uses the page table base address register PTBR and the virtual page number to generate the page table entry address PTEA, accesses the page table stored in the cache/main memory, and requests the page table entry corresponding to the virtual page number.
The cache/main memory returns page table entries to the MMU to form the physical address of the accessed information.
If the valid bit in the returned page table entry is 1, the MMU uses the returned page table entry to construct the physical address PA, and uses the constructed physical address PA to access the cache/main memory.
cache/main memory returns the requested data to the processor.
The page fault handling process is as follows:
The processor generates a virtual address and passes it to the MMU.
The MMU uses the page table base address register PTBR and the virtual page number to generate the page table entry address PTEA, accesses the page table stored in the cache/main memory, and requests the page table entry corresponding to the virtual page number.
cache/main memory returns page table entries to the MMU to form the physical address PA of the accessed information.
If the valid bit in the page table entry is 0, it means that the accessed page is not in the main memory, and the MMU triggers an exception and calls the page fault exception handler in the operating system kernel.
If the main memory page is full, the page needs to be swapped out based on the replacement algorithm. If the page modification bit is 1, the page is swapped out to disk, otherwise it is discarded directly.
The page fault handler loads a new page from disk and updates the page table entry PTE in memory.
The page fault handler returns to the original process, forcing the instruction that caused the page fault to restart. There will be no page faults in this execution.
Virtual memory access process combined with cache
The MMU generates a page table entry address to access the cache based on the virtual address VA sent by the processor.
If the page table entry PTE hits, the page table entry is returned directly and a physical address is generated to access the main memory.
If the page table entry PTE is missing, the page table block where the page table entry is located needs to be scheduled from the main memory to the cache.
There may also be cache missing issues when using PA for data access.
Fast table (TLB)
In a paged virtual storage system that contains fast tables and slow tables, when performing address translation, the fast tables and slow tables are often looked up at the same time.
Access the fast table by content and access the page table by address
TLB hit access process
The processor generates the virtual address and passes it to the MMU.
The MMU uses the virtual page number VPN to query the TLB.
If the TLB access hits (the page table entry is in the TLB and the valid bit in the corresponding PTE is 1), the TLB returns the physical page number corresponding to the virtual page number to the MMU.
MMU uses the returned page table entry (physical page number in) to construct the physical address PA, and uses PA to access cache/main memory.
cache/main memory returns data requested by the CPU to the processor.
Process when TLB misses (assuming access to main memory hits)
The processor generates a virtual address and passes it to the MMU.
The MMU uses the virtual page number VPN to query the TLB.
If the TLB access misses, TLB access miss information is returned to the MMU.
The MMU uses the page table base address register PTBR and the virtual page number to generate the page table entry address PETA, accesses the page table stored in the cache/main memory, and requests the page table entry content corresponding to the virtual page number.
The cache/main memory returns the page table entry PTE to the MMU to form the physical address PA of the accessed information.
If the valid bit in the returned page table entry PTE is 1, the TLB table needs to be updated, and the returned PTE is used to construct the physical address PA, and the constructed physical address PA is used to access the cache/main memory.
cache/main memory returns the requested data to the processor.
Multi-level storage system with TLB and Cache
TLB missing: The page table entry of the page to be accessed is not in the TLB
Page missing: The page to be accessed is not in the main memory (the valid bit of the corresponding page table entry is 0). Corresponding page fault processing: load page, update TLB, restart page fault command
Cache missing: The main memory block to be accessed is not in the cache. Corresponding cache missing processing: transfer from memory and revisit the cache
Segmented virtual memory
Each program sets up a segment table.
Usually, programmers divide different types of data such as subroutines, operands, and constants into different segments, and each program can have multiple segments of the same type.
The segment table entry contains at least the following three fields:
The valid bit indicates whether the segment has been loaded into real memory.
Segment starting address indicates the first address of the segment in real storage when the segment has been transferred into real storage.
Segment length records the actual length of the segment.
address translation
3 abnormal situations
Missing segment (segment does not exist): installed position = 0.
Address out of bounds: The offset exceeds the maximum segment length.
Protection violation, the operation method is inconsistent with the specified access rights.
Segmented virtual memory
Each program performs two-level relocation through a segment table and multiple page tables.
Each entry in the segment table corresponds to a segment, and each entry has a pointer pointing to the page table of the segment.
A virtual address can be viewed as consisting of four fields
A segment table and a set of page tables are used to indicate the location of all pages in virtual memory in main memory.
(Multi-tasking system) Address conversion process of segmented page virtual memory Each program corresponds to a segment table, and each segment corresponds to a page table (there are semantic ambiguities, please refer to the picture).
Comparison between virtual memory and Cache
Similarities
There are issues such as address mapping, replacement algorithm, and update strategy.
the difference
Cache mainly addresses system speed, while virtual memory addresses main memory capacity.
Cache is entirely implemented in hardware and is a hardware memory that is transparent to all programmers. Virtual memory is jointly implemented by the OS and hardware. It is a logical memory that is opaque to system programmers but transparent to application programmers.