Transfer between registers (MOV)

The memory unit reads data into the CPU register (LOAD)

CPU register writes data to memory unit (STORE)

Add (ADD), subtract (SUB), compare (CMP), multiply (MUL), divide (DIV), add 1 (INC), subtract 1 (DEC), AND (AND), or (OR), negate ( NOT), exclusive OR (XOR)

Arithmetic shift, logical shift, circular shift

Loop control instructions

transfer instruction

Subroutine call and return instructions

The difference between call instructions and transfer instructions

When the external device and the main memory adopt a unified addressing mode, there is no need to set up dedicated I/O instructions, and the memory access instructions can be used to directly access the external device.

sequential addressing

skip addressing

MOV EAX,2008H

MOV EAX,[2008H]

MOV EAX,@2008H; @ is the indirect addressing flag

MOV EAX,ECX

MOV AL,[EBX]

EA=PC 1D

Use special registers: The base address register uses implicit addressing method and does not need to be explicitly pointed out in the instruction. The formal address field in the instruction gives the offset value involved in base addressing. Using general registers: You need to add a register number field to indicate the number of the base address register used.

MOV EAX,32[ESI] #Add the offset 32 ​​to the value of the index register ESI to form an address to access the main memory, and send the result to EAX.

memory stack

register stack

The labels used for the operands represent registers, memory, and constants respectively.

data transfer instructions

Arithmetic and logical operation instructions

1) P places the entry parameters (actual parameters) where Q can access them.

2) P stores the return address in a specific place, and then transfers control to Q. CALL instruction

3) Q saves the location of P (the contents of the general register) and allocates space for its own non-static local variables.

4) Execute process Q.

5) Q restores the scene of P, puts the returned result somewhere that P can access, and releases the space occupied by local variables.

6) O takes out the return address and transfers control to P. RET instruction

①Push the old IP value onto the stack (save it at the top of the stack frame of the function) ② Set the new value of IP and unconditionally transfer to the first instruction of the called function

Find the old IP value (i.e. return address) from the top of the stack frame of the function, pop it off the stack and restore the IP register

"Routine processing" at the beginning of each function

"Routine processing" before each function ret

Note: The bottom of each stack frame is used to save the base address of the previous stack frame.

jmp<address> #PC unconditionally transferred to <address> jmp 128 #<address> can be given as a constant jmp eax #<address> can come from a register jmp[999] #<address> can come from main memory jmp NEXT #<address> can be anchored with "label"

Essentially, it performs a-b subtraction operation and generates flag bits OF, ZF, CF, SF

The command system is complex and huge

The length of the instruction is not fixed, there are many instruction formats, and there are many addressing modes.

There are no restrictions on the instructions that can be accessed from memory

The frequency of use of various instructions varies greatly.

The execution time of various instructions varies greatly, and most instructions require multiple clock cycles to complete.

Most controllers use microprogram control

It is difficult to generate efficient object code programs with optimized compilation

Most of them can achieve software compatibility, that is, high-end machines contain all the instructions of low-end machines and can be expanded.

Select some of the most frequently used simple instructions. The functions of complex instructions are realized by a combination of simple instructions.

The instruction length is fixed, there are few types of instruction formats, and there are few types of addressing modes.

Only Load/Store (fetch/store) instructions access memory, and the operations of other instructions are performed between registers.

The number of general-purpose registers in the CPU is quite large

RISC must use instruction pipeline technology, and most instructions are completed within one clock cycle.

Mainly based on hard wiring control, no or less use of micro-program control

Pay special attention to compilation optimization work to reduce program execution time

Most RISC machines are not compatible with older machines